Thursday, March 18, 2010
INTEL ATOM SERIES
Atom Z series
Computer Module based on Intel Atom Z5xx with US15W System Controller Hub.
On March 2, 2008, Intel announced a new single-core processor (code-named Silverthorne) to be used in ultra-mobile PCs/Mobile Internet Devices (MIDs) which will supersede Intel A100. The processor is a 47 million transistor, 25 mm2, sub-3 W IA processor which allows ~2500 chips to fit on a single 300 mm diameter wafer, allowing for extremely economical production.
An Atom Z500 processor's dual-thread performance is equivalent to its predecessor Intel A110, but should outperform it on applications that can leverage simultaneous multithreading and SSE3.They run from 0.8 to 2.0 GHz and have between 0.65 and 2.4 W TDP rating respectively that can dip down to 0.01 W when idle. It features a 2-issue simultaneous multithreading, 16 stage in-order pipeline with 32 KB instruction L1 and 24 KB data L1 caches, integer and floating point execution units, x86 front end, a 512 KB L2 cache and data transferred at 533 MHz on the front-side bus. The design is manufactured in 9M 45 nm high-k metal-gate CMOS and housed in a 441-ball µFCBGA package.
Atom N series
The Intel Atom N270
On March 2, 2008, Intel announced a low-cost mobile processor (code-named Diamondville) to be used in the Classmate PC Netbook. It is used in Intel's low-cost Mini-ITX motherboards (code-named "Little Falls") and in a number of netbooks. It will supersede Conroe L as the N270 (2.5 W TDP) for netbooks and as 230 (4 W TDP) for nettops, each running at 1.6 GHz core speed (both N270 & 230 are single core) with a 533 MHz FSB speed. An N280 with a 1.66 GHz clockspeed and a 667 MHz FSB has since appeared. Both the Atom N270 and Atom N280 are single core processors which support Intel Hyper-Threading Technology.
Atom 300 series
On September 22, 2008, Intel announced a new dual-core processor (unofficially code-named Dual Diamondville) branded Atom 330 of the Atom 300 series to be used in desktop computers. It runs at a 1.6 GHz clock speed and has an FSB running at 533 MHz. The processor has an 8 W TDP rating. Its dual core comprises two Diamondville dies next to each other on a single package (substrate). Atom 330 supports 64 bit instructions.
During 2009, Nvidia used the Atom 300 and their GeForce 9400M chipset on a mini-ITX form factor motherboard for their Ion platform.
ADVANTAGES AND DISADVANTAGES OF INTEL ATOM PROCESSORS
ADVANTAGES
· Low price – suitable for low-cost PC’s and Mobile Internet Devices (MID’s).
· Low Power consumption (lowest in the business).
· Low Thermal Design Power(TDP):
· Low Thermal Design Power enables thinner, lighter, portable netbook devices as it
· Reduces the cooling requirements.
· Power-optimized front side bus .
· Minimizes power needed to transmit data to the processor, resulting in significant power savings and enabling longer battery life - all without impacting performance.
· Intel Enhanced deeper sleep(ie the C6 mode).
· Hyper threading, a good feature on this processor.
· Heavy pipelining.
· Atom offers real internet experience with Flash video, YouTube etc in MID’s.
· Options to include Wi-Fi,Wi-Max,Bluetooth etc.
DISADVANTAGES
· The Chipsets
· Poor 3D performances
· A mismatched platform:
The Menlow platform is a little too large, too power-hungry, and too PC-centric to really deliver on Silverthorne's potential. Once Silverthorne-derived Moorestown system-on-chip arrives, and then we'll see the really sweet devices based on this processor technology come out of the woodwork. Moorestown is the Intel Corporation's code name for successor to the Menlow platform designed for mobile Internet devices. Current proposals call for it to use 10 times less power than Silverthorne and to hit the market in 2009-2010.
COMPARING INTEL ATOM AND CORE 2 PROCESSORS
The recently released Intel® Atom™ architecture utilized the same basic data flows as the Intel® Core™ 2 Duo architecture, but instead of just the MCH and ICH, the Intel® Atom™ processor can connect to a System Controller Hub (SCH). The SCH integrates most of the MCH and ICH functionality into one device that optimizes the interfaces for ultra low power applications. The target markets for the SCH do not require the same number of ports on each interface that the ICH can provide. For designs based on the Intel® Atom™ processor, there is also a version of the MCH/ICH that can work with the Intel® Atom™ CPU to provide the large quantity of I/O ports, if it is needed. The SCH provides a similar power management role as the ICH and should be powered first. The basic components that make up the Intel® architecture system are the CPU, memory controller, and I/O controller. Supporting these components are non-volatile memory, power supplies, and some glue logic.
The components shown are:
• IOH – I/O Hub
• ICH – I/O Controller Hub
• SCH – System Controller Hub
• MCH – Memory Controller Hub
The interfaces shown are:
• FSB – Front Side Bus
The Intel® Atom™ processor design is optimized for very low power consumption. The voltage levels are lower and the speed of the FSB is lower than the Intel® Core™ 2 Duo. The lower speed FSB allows CMOS drivers to be used which draw less power than the GTL drivers. Another capability of the Intel® Atom™ CPU is to dynamically reduce on chip cache size to save power.
The SCH has many advanced power management capabilities to enable the lowest possible platform power consumption
Memory Controller
The central hub for the data traffic in an Intel® architecture system is the Memory Controller Hub (MCH). Until the new Intel® Atom™ and Intel® Core™ i7 architectures were developed, the MCH had been a discrete component. The Intel® Core™ 2 Duo architecture uses a discrete MCH which will be described first. shows the MCH for a system featuring the Intel® Core™ 2 Duo processor. The MCH facilitates the transfer of data to and from all the interfaces. When the BIOS configures the MCH, it defines the base address locations for all the interfaces. The BIOS relays the configuration information to the operating system so it knows the capabilities and locations of the hardware that is in its system.
There are many different models of MCH currently offered by Intel. The feature differences between MCH’s include the number and type of memory channels, the number of PCIe* lanes supported, internal 2D/3D graphics, single or multiple CPU support (uni-processor (UP) or dual-processor (DP) or multi-processor (MP)). Intel validates specific CPU’s with specific MCH’s to provide a well balanced platform. Not all CPU FSB speeds are compatible with all MCH.
fig:MCH
The CPU connects to the MCH through the FSB which was described earlier. The FSB unit in the MCH is responsible for the CPU cache coherency. If data at the address requested is not in the CPU cache, or the data in memory is newer, the memory controller is told to retrieve the data at that address. Data transfers between the CPU and memory are always 64 bits, the full width of the L2 cache on the CPU. If only a byte of data is requested, the full 64 bits is retrieved but the CPU will only use 8 of those bits. The memory controller is configurable by the BIOS to support multiple speeds and sizes of memory. The refreshing of the DRAM is handled by the memory controller after it’s initially configured. The specific type, size, and speed of memory that is supported, varies by the model of MCH. The Direct Media Interface (DMI) interface in the MCH is a dedicated serial link to the I/O Controller Hub (ICH). The DMI link is actually four serial links, with dedicated transmit and receive pins. These serial links are referred to as “lanes” and all use differential signaling. So the DMI is 4 lanes x Transmit and Receive (2) x differential signaling (2) = 32 pins. The DMI usage will be described in a separate section.
DMI supports signaling of 2.5GT/s. The PCI Express* (PCIe*) interface is the highest bandwidth I/O interface in the IA system. The number of PCIe lanes can vary depending on the MCH used, but will usually be in multiples of 8. A common width for PCIe is 16 lanes as this is the maximum width for discrete PCIe graphics cards. The PCIe interface uses the same differential signaling that the DMI does, but PCIe supports higher transfer rates. The original PCIe specification states data rates of 2.5 GB/s per lane (this what DMI uses). The second generation of PCIe is now available and doubles the data rate to 5Gb/s. Many of the MCH versions also have internal graphics controllers. The details of the graphics controllers won’t be covered in this document, but the basic capabilities are 2D and 3D acceleration. The type of display interfaces directly supported by MCH’s varies by the model.
I/O Controller
The I/O Controller Hub (ICH) provides extensive I/O support, support for legacy peripherals dating back to the 1980s, and integrates support for key platform management functions such as power sequencing and ACPI power management, fan speed control, and reset timing. It will be seen that these later functions are critical to system operation and often overlooked by designers.
fig: ICH
As the ICH is used to control the reset sequence, and often power sequencingof the other system components, it has power supplies which are required to turn on before the rest of the system. Also, the Real Time Clock (RTC) needs to have a 32.768KHz oscillator running before to properly sequence. The ICH communicates with the IOH/MCH during reset and power cycling events to try to make these events “safer”. For example, a warning message will be sent over DMI before a reset to allow SMBUS or memory transactions to complete before the reset.
Modern I/O interfaces
The ICH acts a bridge or controller for a variety of industry standard interfaces allowing the system designer to choose from a wide range of peripherals.
• PCI interface operates at 33MHz and allowing for a number of external bus masters. The ICH acts as the central arbiter and root of the PCI bus.
• PCI Express* root port controllers. The number of ports varies with the product but is generally in the range of 1 to 4. Link widths of x1 x4 are support at speeds of 2.5GB/s.
• Serial ATA (SATA) controllers supporting both legacy operation using I/O space and the Advanced Host Controller Interface (AHCI) using memory mapped I/O as well as allowing advanced features such has hot-plug and native command queuing. SATA II supports data
rates of 1.5Gb/s and 3Gb/s.
• Integrated Drive Electronics (IDE) controllers are also used to control hard disc drives, and CD/DVD drives. They have been replaced in some platforms by the newer SATA interface since it offers better performance over a smaller interface.
• Universal Serial Bus (USB) supporting High Speed USB 2.0 (480 Mb/s) operation as well as full-speed (12 Mb/s) and low-speed signaling.
• General Purpose I/O (GPIO) pins for system customization. Many pins can also be configured to cause interrupts or wake events.
• System Management Bus (SMBus 2.0) The SMBus Host interfaces allows the processor to communicate with SMBus slaves. This interface is also compatible with most I2C devices. Slave functionality, including the Host Notify protocol is implemented. Hence, the host controller supports eight command protocols of the SMBus interface (see System
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
• Serial Peripheral Interface (SPI) is used to interface to BIOS flash devices which contain the boot firmware and initialization code. Up to 2 SPI flash devices operating at 33 MHz can be connected. Note that the flash devices connected to the LPC interface are quickly becoming obsolete and SPI is expected to be standard interface for BIOS flash in the future. The ICH is always a master on the SPI interface.
• Low Pin Count Interface (LPC) This interface replaces the ISA bus originally developed by IBM in the early 1980s, but uses only 7 signals plus a clock. It can be used to connect to a variety low speed devices that don’t require the bandwidth of PCI or PCI Express*. This interface is typically used to interface with Super I/O devices which contain many interfaces such as floppy driver controller, PS2 keyboard/mouse controls and serial ports.
• JTAG Boundary Scan allows testing of PCB board after assembly.
Support peripherals
The ICH integrates numerous support peripherals that replace many external components.
• Real Time Clock (RTC): The RTC is compatible with the Motorola MC146818A*. It contains 256 bytes of RAM that can be maintained with a 3V battery. 242 bytes are available for use while the remaining is dedicated to the clock function. The RTC supports generating wake events up to 30 days in the future. An external 32.768 KHz crystal is required for operation.
• High Precision Event Timers These are high resolution timers which can be used to generate periodic or one-shot interrupts. There are 8 comparators which share a common counter that is clocked from a MHz source.
• Advanced Programmable Interrupt Controller (APIC) is a more modern interrupt controller than the 82C59 (see below). It supports multiprocessor/multi core interrupt management and allows interrupts to be directed to a specific processor. The I/O APIC in the ICH can support up to 24 interrupt vectors and can work in conjunction with I/O APICs in other devices (such as the IOH) to help eliminate the need for multiple device to share interrupts. – flat panel display interface.
SYSTEM CONTROL HUB
fig :SCH
The I/O and peripheral interface differences between the ICH and SCH are listed below.
• SDIO Secure Digital Input / Output – Usually used for media cards.
• MMC Multi-Media Card – Usually used for media cards.
• SDVO Serial Digital Video Out – display interface.
• LVDS Low Voltage Digital Signaling – flat panel display interface.
FEATURES OF INTEL ATOM PROCESSORS
1 Small form factor cpu package
The new lead-free², halogen-free³ Micro-Flip Chip package is 60% smaller in netbooks (22x22 mm) than a notebook CPU (35x35 mm), saving system board real estate in a much thinner and smaller industrial design, enabling small netbook form factors.
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2 Intel® enhanced deeper sleep
Power consumption is central to this Intel platform, and they’ve made a lot of efforts in that department. Aside from the chipset, which consumes a lot of power in comparison to the processor, the Atom itself has many attractive functions.
C6 power state
In addition to the low voltage (1.05 V) CPU, the Atom also introduces a new standby mode, C6. As a reminder, the C modes (0 to 6) are low-power states, and the higher the number, the less the CPU consumes. In C6 mode, the entire processor is almost totally disabled. Only a cache memory of a few kB (10.5) is kept enabled to store the state of the registers. In this mode, the L2 cache is emptied and disabled, the supply voltage falls
to only 0.3 V, and only a small part of the processor remains active, for wake-up purposes. The processor can go into C6 mode in approximately 100 microseconds, which is quick. In practice, Intel claims, C6 mode is used 90% of the time, which limits overall power consumption (obviously, if you launch a program that requires a lot of CPU power or even watch a Flash video you won’t be in that mode).
We should point out, though, that the two chipsets to be used with the Atom N200s are power users: the Atom 230s use a i945GC that consumes 22 W (4 W for the CPU) and the Atom N270s ship with a i945GSE that burns 5.5 W (2.4 W for the CPU)
3 Power-optimized front side bus
The Atom’s FSB is the same one used by Intel since the Pentium 4. It operates in Quad Pumped (QDR) mode with GTL signaling. An interesting point: The Atom uses another signaling technology – CMOS mode. GTL is effective (the bus can reach 1,600 MHz), but power-intensive, whereas CMOS allows the bus voltage to be reduced. Technically, GTL uses resistors to improve the quality of the signal, but they aren’t really necessary except at higher frequencies. With the Atom and its bus, limited to 533 MHz, it’s possible to change to CMOS mode – the resistors are deactivated and the bus voltage is reduced by half. At the moment, only the SCH chipset is capable of handling the FSB in CMOS mode
4 Intel smart cache
Cache is an important system that impacts overall system performance. A pc with larger cache allows more data to be accessible from that faster storage area, increasing performance and responsiveness. Processors with greater cache can benefit most applications-from running rich media titles and games to everyday productivity applications. Intel SmartCache increases the probability that each processor core can access data from the faster most efficient subsystem. Intel SmartCache allows each core to dynamically utilize up to 100% of available cache, while obtaining data from the cache at higher throughput rates
5 Low TDP
Low Thermal Design Power enables thinner, lighter, portable netbook devices as it reduces the cooling requirements.
6 Enhanced speedtech technology
Enhanced Intel SpeedStep Technology allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production. By decreasing power and heat on desktop PCs, system builders can (depending on system configurations) potentially lower acoustics, and even develop more innovative small form factor designs. Additionally, this feature can help address power concerns in companies with sites approaching the limits of bounded electrical infrastructures. Combined with existing power saving features, Enhanced Intel SpeedStep Technology can provide an excellent balance between providing power when you need it and conserving it when you don’t
EIST ON
If Enhanced Intel SpeedStep Technology is enabled, two processor speeds will be listed. The first speed listed is the specified speed of the processor. The second speed is the current operating speed. The second speed will be less than the first speed. This indicates that Enhanced Intel SpeedStep Technology has effectively lowered the processor voltage and core frequency, which can (depending on system usage and design) result in decreased average power consumption and decreased average heat production. If Enhanced Intel SpeedStep Technology is off, then both processor speeds will be equal If the processor is not in idle mode, Enhanced Intel SpeedStep Technology can be enabled and both processors speeds can be equal.
EIST OFF
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